1. Field of the Invention
The present invention relates to techniques for analyzing timing in circuits. More specifically, the present invention relates to a method and an apparatus for speeding up timing analysis by reusing delays computed for isomorphic subcircuits.
2. Related Art
Circuit design is presently accomplished primarily through the use of computer aided design (CAD) tools, which take as input a circuit specification and automatically generates a circuit description suitable for implementation. This circuit description can subsequently be analyzed using a number of different techniques to estimate the performance of the circuit before the circuit is fabricated. This allows the design of the circuit to be modified to correct performance problems before the circuit is actually fabricated, which can greatly reduce the time and expense involved in the circuit development process.
Unfortunately, these circuit analysis techniques are often too expensive to be applied to a large number of circuit elements at once. To reduce this complexity, a circuit is typically subdivided into smaller subcircuits, and the analysis technique is applied to each subcircuit. Next, results from analysis of subcircuits are combined to create a solution for the entire circuit. For example, in the transistor-level static timing analysis problem, circuits are often subdivided into channel-connected subcircuits, which are individually analyzed for timing. The analyzed delays for these subcircuits are combined to determine the timing for the larger circuit.
While this subdivision technique reduces the overall complexity considerably, the analysis of the individual subcircuits, which often involves time-consuming circuit-simulation operations, can dominate the total time required to validate the timing of the entire circuit. For example, in the standard-cell design methodology, the process of characterizing a library of cells for timing often takes orders of magnitude longer than gate-level static timing analysis of a large block constructed of the library of cells. In another example, in the custom design methodology, the transistor-level static timing tool typically spends over 85% of its time deriving delays for the subcircuits comprising the custom block.
Hence, what is needed is a method and an apparatus for analyzing the performance of a circuit without the above-described performance problems associated with analyzing the individual subcircuits.